Synchronous memory devices represented by synchronous DRAM (Dynamic Random Access Memory) have been widely used for a main memory or the like of a personal computer. The synchronous memory device can input and output data in synchronism with a clock signal supplied from a memory controller. Therefore, when a higher-speed clock is used, a data transfer rate can be increased.
However, so long as a DRAM core performs an analog operation also in the synchronous DRAM, a considerably weak charge needs to be amplified based on a sense operation. Accordingly, it is not possible to shorten a time from issuing a read command until outputting first data. After a lapse of a predetermined delay time since an issuance of the read command, the first data is outputted in synchronism with an external clock.
This delay time during a read operation is generally called a “CAS latency” and is set to an integral multiple of a clock cycle. For example, when the CAS latency is 5 (CL=5), the synchronous memory device fetches the read command in synchronism with the external clock, and thereafter, outputs the first data in synchronism with the external clock after five clock cycles. That is, the first data is outputted after a lapse of the five clock cycles.
Such delay is required also during a write operation. During the write operation, the data needs to be continuously inputted in synchronism with the external clock after a lapse of a predetermined delay time after an issuance of a write command. This delay time during the write operation is generally called a “CAS write latency” and is set to an integral multiple of a clock cycle. For example, when the CAS write latency is 5 (CWL=5), the synchronous memory device fetches the write command in synchronism with the external clock, and thereafter, needs to input the first data in synchronism with the external clock after five clock cycles.
The write data thus fetched is written via a read/write bus, a column switch or the like into a memory cell employed inside the memory device. Thus, it is necessary that an address signal is appropriately delayed also inside the memory device to supply the address signal to each circuit at an appropriate timing. Because of these purposes, an FIFO circuit that delays the address signal by a predetermined period is used in the synchronous memory device. Such a FIFO circuit is generally called an “address counter”.
The most simple method for delaying the address signal is to use a shift-register FIFO circuit. However, when this method is used, there is a problem in that since the number of required stages of shift registers is proportional to the latency. Therefore, when the latency becomes larger, a size of a circuit scale is automatically increased. Since the latency is tended to become larger with a higher frequency of a clock, it is not possible to avoid an increase of latency caused concurrently with a high speed of the synchronous memory device.
For an FIFO circuit smaller in circuit scale than that of the shift register type, there have been types of a point-shift FIFO circuit described in Japanese Patent Application Laid-open No. 2007-102936 and in “A 1.2 Gb/s/pin Double Data Rate SDRAM with On-Die-Termination”, by Ho Young Song and 15 others, ISSCC 2003/SESSION 17/SRAM AND DRAM/PAPER 17.8, (U.S.A), IEEE, 2003, p. 314. The point-shift FIFO circuit is an FIFO circuit which has a configuration in which a plurality of latch circuits having input gates and output gates are connected in parallel. The point-shift FIFO circuit can set an output timing of a latched signal by being brought any one of the input gates and any one of the output gates into on state.
The number of latch circuits required for the point-shift FIFO circuit is not equal to that of the latencies, but is defined according to a maximum accumulation number of an address signal to be delayed. Thus, the circuit scale can be further reduced than a case that the shift register is used.
As described above, in the synchronous memory device, timings for supplying addresses to the respective internal circuits differ. Thus, when the address counter is configured by using the point-shift FIFO circuit, it becomes necessary to prepare a plurality of sets of FIFO units inside the point-shift FIFO circuit.
More specifically, because write data inputted via a data input/output terminal is supplied from the data input/output circuit via the column switch or the like to the memory cell, supplying the address signal basically needs to be performed according to this order. Thus, it becomes necessary to separately prepare a FIFO unit that supply the address signal to the data input/output circuit and a FIFO unit that supply the address signal to the column switch.
In addition, as described above, the number of latch circuits required for one set of the FIFO unit is defined by a maximum accumulation number of address signal, and thus, when a minimum input cycle (tCCD) of a command is small, the circuit scale becomes large as a result, and this poses a problem.